There is a lot of interest in FPGA and ASIC in the HFT/quant industry at the moment.
This is unsurprising as the industry incentivises "race to zero [latency]".
Does anyone have any insight they can share, particularly with regard to compensation in this roles, relative to "risk taking" positions?
This is unsurprising as the industry incentivises "race to zero [latency]".
Does anyone have any insight they can share, particularly with regard to compensation in this roles, relative to "risk taking" positions?
